Electronic digital computing machines



Nov, 27, 1956 A. A. ROBINSON Erm. 2,772,050

ELECTRONIC DIGITAL COMPUTING MACHINES 5 Sheets-Sheet 1 Filed June 2l, 1950 Nov. 27, 1956 A. A. RQBINSON ETAL 2,772,050

ELECTRONIC DIGITAL COMPUTING MACHINES 5 Sheets-Sheet 2 Filed June 2l, 1950 ...una mmm EE #ad @MN mwrr QQ hm..

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ELECTRONIC DIGITAL COMPUTING MACHINES Filed June 21, 1950 5 Sheets-Sheet 5 D/V (il) n/v2 fill? BLACK our (IV) DASH :Kl/U

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ELECTRONIC DIGITAL COMPUTING MACHINES Filed June '21, 195o 5 Sheets-Sheet 5 INVENTORS.

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United States Patent O ELECTRONIC DIGITAL CNIPUTING MACHINES Arthur Alexander Robinson, Scunthorpe, Frederic Calland Williams, Timperley, and Tom Kilburn, Manchester, England, assignors to National Research Development Corporation, London, England, a corporation of Great Britain Application June 21, 1950, Serial No. 169,386

Claims priority, application Great Britain `lune 2'2, 1949 4 Claims. (Cl. 23S-61) The present invention relates to electronic digital computing machines involving the use of storage or memory devices of the type described in copending applications of Frederic C. Williams, Serial No. 790,879, led Dec. 10, 1947; Frederic C. Williams et al., Serial No. 50,136, led Sept. 20, 1948 and Frederic C. Williams et al., Serial No. 124,192, led Oct. 28, 1949, now Patent No. 2,527,336. As described in these speciications, information is stored on the screen of a cathode-ray-tube in the form of a charge pattern which is regenerated by being repeatedly scanned by an electron beam which is modulated by signals obtained from and characteristic of each unit or digit representing section of the charge pattern.

This simple regeneration process which is described in copending application of Frederic C. Williams et al., Serial'No. 93,612, filed May 16, 1949, is carried out by means of a regeneration circuit in which a pick-up electrode associated with the cathode-ray-tube screen supplies signals which determine the nature of the further signals used to control the irradiation of the screen.

Copending application of Frederick C. Williams, Serial No.ll9,306, filed Oct. 3, 1949, now Patent No. 2,671,607, issued March 9, 1954, describes the provision of a computing circuit within the regenerative loop and which is adapted to receive signals from the pick-up electrode and also from an external source and to provide resultant signals for supply to the means used for controlling the irradiation of the tube screen.

The signals from the pick-up electrode and the signals from the external source may be required to be combined in various ways according to the type of mathematical process which is required to be carried out. For instance, two numbers, represented respectively by the signals received from the pick-up electrode and from the external source, may be required to be added, subtracted, multiplied or divided. The provision of a subtracting circuit in the regenerative loop in the manner described in the aforesaid copending application, Serial No. 119,306 now Patent No. 2,671,607 would enable a considerable number of different operations (in addition to plain subtraction) upon the two input signals to take place under the control of a programme of instructions. In order to enable any of a large number of arithmetical operations to take place, however, the number of instructions involved in each operation would have to be of great complexity and would require relatively long intervals of'time for their completion when only one form of arithmetical or computing circuit is provided.

lt is one object of the present invention to providea regenerative circuit of the type set forth in which a numberl of different forms of computing circuits can be connected at will into the regenerative loop so that any of a number of standard mathematical operations can be performedV as desired and the associated programme of instructions can accordingly be much simpler than would otherwise be necessary.

According to the present invention, therefore, appaice ratus as claimed in patent application No. 119,306, now Patent No. 2,671,607, and comprising a cathode-raytube storage device having a storage screen, an assoclated pick-up electrode, means for controlling the irradiation of said screen and a regeneration circuit between said pick-up electrode and said controlling means, has said regeneration circuit arranged so as to include a plurality of computing circuits and switching means by which any one of said computing circuits may be alternatively switched into the regeneration circuit so that the signal supplied to said controlling means may be the result of any chosen one of a number of computing operations performed upon vthe signal from the pick-up' electrode of said tube and a signal supplied from an external source.

ln order that the inventionl may be more clearly understood one embodiment thereof will now'be described with reference to the accompanying drawings in which:

Figs. la and lb show in block schematic formthe various essential components of an electronic digital computing machine embodying the invention.

Figs. 2 and 3 illustrate by means of diagrams, a series of fundamental voltage waveforms which are available within the machine of Figs. la and lb.

Fig. 4 is a detailed circuit diagram of one section of a staticisor device shown in Fig. 1, while Fig. 5 -is a detailed circuit diagram of one suitable form of switching or gate circuit usable for controlling the operation of the computing circuits.

Fig. 6 is a fragmentary circuit diagram showing a modiiication of the accumulator of Fig. l.

Referring rst to Figs. la and lb, the `machine thereshown is a simplified version, apart from the special construction of the computing arrangements to be described later, of that already described inV detail in Figs. la and lb of copending application of Frederick CL Williams et al., Serial No. 165,434, tiled June 1, 1950 to which further reference should be made when detailed information is desired. v

This machine operates under the binary system andV is of the serial type. It utilises for various memory or storage purposes cathode ray tube Vstorage means of the kind described, wherein each binary digit 0 or 1 of a number or the equivalent coded address or instruction word is represented by one or other of two, e. g. dot or dash forms of discrete electric potential charge upon the screen of a cathode ray tube. The group of sequential dot and dash charges comprised in each number or Word are arranged along the whole or part of a single linear deection scan of the cathode ray tube beam so that, when required, a plurality of such numbers or words may be recorded and stored side by side, by causing the beam to provide a television type raster. Selection of any desired number or word can then be achieved by arranging for.

the appropriate positioning of the tube beam vin the transverse or Y direction before commencing its linear or X scanning movement.

The machine shown in Figs. la and lb comprises aV Main store MS which includes one or more cathode ray tube storage devices as referred to above arranged forO side-by-side or raster type line storage and provided with the necessary ancillary apparatus by which numbers or' the previous address section ofthe word.

the main store and whose function is to translate a dynamic pulse form signal into suitable static control voltages for the unit YSG whereby the'lattrer provides a dellection of the tube beam in the main store MS toa raster line whose address4 isfthat indicated Yby the pulse Signal fed to the staticisorV unit.

VThe arithmetical operations upon either number or 1nstruction words are effected in the Arithmetical` organ or Accumulator `A which will be described'in detail later andV which includes a single cathode ray Vtube storage Vdevice Varranged to vdeal with'onlyone number or word at a time and provided Vwith the requisite writing, reading, erasing and regenerating ancillary apparatus. Y

` :The control of the various elements of -the'machine during eachbar in obedience to the particular instructionY of the moment isV effected by Ithe control unit CL which includes a` single cathode ray'tubegstorage device arranged for vtwo-line storage and'provided with therequisite an- Y cillary apparatus forceffecting writing in, reading out,

erasing 4and regenerating Veach of the two stored words. This ancillaryapparatus alsoV includes Vmeans by which an externally applied number, Yin the form of a pulse signal, may 'beradded to a word already in the store.

The necessary transverse or Y-deection of the beam of struction word at the end of Veach barV so that thevarious During automatic operation on the first (Scanjl)v beat Yregeneration Vtakes place in Vall storagezunitsandwhile it Yisdoing so in the control unit CLJa control instruction 'i sequential operations Vas `defined by the'programme laidV down for Ythe machine are effected in order the Test Unit TU is Vprovided and serves, in combination with ancillary adding'apparatus ofthe control unit CL, normally, toV add 1 to the address number of a word stored in the latter. ThisV test unit TUV also comprises means for determining the compliance or otherwise of a solution number existing within Vthe accumulator A with a certain requirement, e. g. of its sign, and dependent upon the result of such test, for altering the aforesaid addition Vof l to an addition of 2 to the address number within the control unit.

The routing ,of the various signals between units of the Vmachine and the choice of its manner of operation are controlled through the intermediaryV of a number of gate orqequivalentV circuits among which are the YInward Transfer Gate ITG, the Outward TransferV Gate OTG and the Instruction Gatev IG. These, gates and other circuits are controlled by the s-tatic voltage levels provided at different terminals of a further portion, the F Staticisor unit FST, ofthe staticisor MSTR and which, in similar manner to the L-staticisor LST is itself controlled byY portionsrof the dynamic pulse form signal fed thereto.

In broad outline the operation of the machine is asV follows:

Number words related to the mathematical quantities being dealt with within the machine will consist of an appropriate collection of binary digits upto the maximum capacity of one line of the storage tube which, in thisY Case, is forty digits. f t Y The instruction words within the machine will in geni eral comprise two separate sections, the first consisting of a group of binary digits, which are related to andk serve to signal the particular address, i. e., the particular line or Y-level in the main store MS at which a desired number word is located and a second section, again composed of a collection of binary digits which serve to signal and control the nature of the function which is required to..be carried Vouton the kparticular number chosen by In general 2,772,050 f 'Y Y witha machine ofthe simplest type descri-beilaV iivebinarydigit symbols will suffice to select any desired address level while a total of iive binary digitV symbols is' Vsufiicient to set up any of the different function operations which can becarried out; VAccordingly, the lst, 2nd, 3rd, 4th' and 5th digits of the word are used to signal the address and the 14th, 15th,` 16th, V17th and `18th-digits Y to signal the functionaloperation. Y

Assuming all the required number and address -words have been inserted in the main store MS'thcn the normal automatic operation cycle is ras follows. ,.Each'bar will be initiated by a prepulse from the propulse unitvBPU.

number (n) already stored in, control unit CL on one,

the CI line, of itsjtwo levels will berlincreased by l auto- Y matically by a pulse sent out from the ltest unit TU and the resultantV new number (n+1) `simultaneously `read out of the control unit CL through the opened instruction t gate IG to the VL-staticisor LST where the lst to 5th digits i of the number will set such L-staticisor to a condition which provides a seriesof static output voltages forrconi trolling t e Y-shift generator YSG during the next fol# lowingV (action) beat such as will adjust theYY-level of the main store MS during that action beat -to that of the Y next instructionnumber which is to be read out..from the main store MS. Y t VOn the next (Action 1) beat there is no regeneration anywhere but the newly selected ,or Present Instruction number is read out from the main store MS Ythrough the opened Voutward transfer gate OTG into the store CLV at the alternative or P. I. level of the latter. The beam kscanning level ofthe storage tube of thisV unit is suitably altered'by a `waveform suppliedfrom the unit GYWG.v

In' the next following (Scan 2) beat, the'new, Present Instruction word in the store CL is readout through the instruction gate IG to theV Irl-staticisor FST and thel.- staticisor LST. The F-staticisor isV operated bythe V14th` 18th digits of Ysuch word toprovide a series Vof different voltages which lwhen applied to the various circuit Velements such as the inward and outward transfer gates ITG and OTG the erase, writing, adding,.subtracting, or reading circuits of the'various store unitsrand, as described later, elements of the Accumulator A, serve to setup the necessary routing andcontrol arrangements for the particular function operation next to be performed. The .l

addressY` digits i. e. the list toSth digits of the same word cause similar operation in the L-staticisorV LST to reset the' Yscan generator ofthe main store4 MS to the particular new level of the number stored in the main store MS which is next Yrequired to takepart in the chosen operation.

l In Ythe fourth (Action 2) beatl the Vaforesaid Present'- Instruction is obeyed by the transference of the selectedY number out of the main store MS over the particular path and through the operation of the appropriate other units asselected by the F-staticisor FST to a destination which Y will normally be the accumulator A.

In the next following operation the tion (n4-1)l previously existing at the firstV level in the unit CLis again increased by l whereupon the cycle'is repeated substantially along theV lines described. By arf ranging that the Vsuccessive present instruction words read out fromY the main store define the required programme of operation, the required computation will'be completed automatically.

The basic timing of the machine' shown in Figs. Vla, andY lb is controlled by a pulse generator circuit'CPGwhich provides a series, of square pulses whose period Vtime is 8.5 microseconds. Y Y of Fig. 2 will hereinafter be called Clock Pulses. The time period ofa total of of these Clock pulses isV assigned to each beat .of the machine .and'of vthis period the time requiredby 5 Clockpulseslis Vassigned t0 the trax of Y control instruc These pulsesshown in diagram (i) i requisite yback motion of the beam of each cathode ray tube storage device before each linear scanning motion leaving a total of 40 Clock periods for the actual composition of each number or word. Each digit of a number or word is arranged to fall within the period of l Clock pulse and the machine therefore has a capacity as already stated of 40 digits in each number or word.

The Clock pulses are applied to a divider circuit DV1 which can be of any suitable form to provide an output pulse for every tive input pulses as shown in waveform (ii) of Fig. 2. These pulses will hereinafter be called the DIVI pulses and are then applied to a further divider circuit DVZ which again is of any suitable form Vto provide an output pulse for every nine input pulses as shown in wave form (iii) of Fig. 2. These pulses, which occur one in synchronism with each 45th Clock pulse will hereinafter be referred to as the DIVZ pulses.

The pulses from divider circuit DVI are applied as one triggering input to a liip-op circuit BOPG, the other triggering input of which is supplied from the divider circuit DV2 by way of a gate circuit G1 which is opened by the further supply thereto of the pulses from the divider circuit DVI. The consequential output from circuit BOPG, is a waveform as shown in diagram (iv) of Fig. 2, consisting of positive going square pulses during the period of Clock pulses l to 5 and then a quiescent period until the end of Clock Pulse 45 and so on. This waveform which is used to ensure suppression of all the cathode ray tube beams during the tiyback time following each line scan, will hereinafter be called the Black- Out waveform.

vThe requisite repetitive saw-tooth waveforms for causing linear scanning movement of the various cathode ray tube beams in the X direction are provided by the X-tme base generator XWG which is controlled by the Black- Out waveform so that the flyback portion commences at the instant of commencement of each positive going Black-Out pulse and the linear scanning portion at the instant of termination of each Black-Out pulse.

The setting up of one or the other of the two dierent forms of discrete charge upon the cathode ray tube screens, representative respectively of the binary digits and "l is etected by intensity modulation of the tube beam for time periods of dierent lengths whereby, due to the concurrent X scanning movement of the beam, a dot or a dash charge pattern is provided. For eecting such beam modulation the machine is provided with a dot pulse generator DTPG and a dash pulse generator DSPG each of which are supplied with the Clock waveform to initiate triggering of suitable pulse generating circuits, the constants of the circuit of DTPG being such as to provide a series of two microsecond negative-going pulses each coincident in their commencement with the leading edge of a Clock pulse as shown in diagram (v) of Fig. 2 and the corresponding constants of the circuit of DSPG being such as to provide a series of five-microsecond pulses each coincident in their commencement with the leading edge of a Clock pulse as shown in diagram (vi) of Fig. 2. By supplying the output from each of the circuits DPTG and DSPG through Gate Circuits G2 and G3 which are controlled by an output from the Black-Out waveform generator BOPG the Dot and Dash pulses are inhibited during the time of the first five Clock pulses of each complete beat of 45 pulses so as to provide series of separate groups of Dot and Dash pulses, 40 in number, and each coincident in time respectively with Clock pulses 6 to 45. These Dot and Dash waveforms are conveniently made available through buffer ampliers BAi, BA2.

In order to allow selection of specific ones of said Dot or Dash pulse series and for other similar purposes there are provided a group of 40 single pulse waveforms, each on separate leads and each consist of a single microsecond pulse coincident in timing with one or other of the Dash pulses. These waveforms will hereinafter be referred to as the p pulses and diagram (viii) Fig. 2 shows the rst of the group comprising a negative-going pulse synchronised in time with the first Dash pulse and called, for convenience in computing, the p9 pulse since it coincides with the position in the group of 40 pulses, of the lowest significant gure 2 in the binary scale (for convenience, the order of signicance of the digit positions is assumed to increase from left to right). The next pulse of the group, the p1 pulse (denoting 21 in the binary scale) is shown in diagram (ix) Fig. 2 and is coincident in time with the second Dash pulse while `diagrams (x) and (xi) respectively illustrate the next or p2 pulse (22) and the last or p39 pulse (239). The intervening pulses of the group are not shown since their form will be obvious. These p pulses are conveniently produced by a series of triggered circuits vPPG all of which are supplied with the Dash waveform. Normally each circuit is in inoperative condition and produces no output but each can be conditioned for operation by the application of a positive transient voltage in readiness to provide an output pulse coincident with the arrival thereat of the next Dash pulse. The iirst trigger circuit po of the series is conditioned by the application thereto of the lBlack-Out waveform while the subsequent trigger circuits pl to p39 are each conditioned by voltages derived from the immediately preceding circuit. The last circuit p39 is reset by the leading edge of the next following Black-Out pulse from the circuit BOPG.l

The reading or interpretation of an already stored charge pattern on a cathode ray tube screen is eiected by sampling a portion only of each discrete charge as the cathode ray tube beam is sweeping thereacross and for the purpose of controlling such sampling or reading instants a further series of pulses, hereinafter called the Strobe pulses are provided. These pulses which are shown in diagram (vii) Fig. 2, are positive-going and have about one microsecond duration commencing at instants slightly later than the leading edges of the Dot and Dash pulses. They are derived in the circuit shown from a pulse generator circuit SPG triggered from the Clock pulse Waveform and fed, in similar manner to the Dot and Dash pulses, through the gate circuit G3, controlled by the Black-Out pulses, to a buifer amplifier BAS.

As already referred to, the natural decay of the cathode ray tube charge patterns with time, owing to leakage necessitates their frequent and repeated regeneration and this is effected where necessary in the machine described by assigning alternate X-time base scans to regeneration and using the intervening scans for operational purposes. These periods are those known as the scan and action beats respectively, each four beat bar therefore comprising a scan 1 beat, an action 1 beat, a scan 2 beat and an action 2 beat. For the purpose of etfecting control of various elements during these alternate beats, two further square waveforms, at half the frequency of the Black-Out and XTB waveforms are provided as shown in diagrams (xii) and (xiii) of Fig. 3. They are derived from square wave generator circuit HWG comprising a tiip-flop circuit triggered from one state to the other by the Black-Out waveform. One output comprising positive-going half cycles coincident with the scan beat periods will hereinafter be referred to as the Halver-S waveform while a second paraphase output having its positive-going half cycles coincident with the action beat periods will hereinafter be referred to as the Halver-A waveform. Fig. 3 is drawn to a time-scale four -times smaller than that of Fig. 2 to illustrate the four beats of one operative cycle or bar. For comparison purposes the Black-Out waveform is reproduced while diagram (xiv) illustrates the Prepulse Waveform which controls the initiation of each bar.

A number of other waveforms are involved in the machine but the form and production of these Will not be dealt with here since they are not involved in the operation of the particular elements concerned with the present invention.. Afulldescription thereof*4 is, however,

to. befound. in.Y the aforesaid. copending.; application, Serialv No...165,434.1..Y j Y Thepresent. inventionZ resides. in the provision of a spgeciaLform1 of. accumulator A which,l as shown in, Figs. Y

1a.. and. 1b, .has in. addition to its storage. tube. 16 with pickup. electrode 17, amplifier 13,- read unit 1-9, write 'unitn 20 and other-ancillary items, .a pluralityy ofV com-V puting circuits 2122 and23 each having. first and second input terminals and an. outputterminal and connected by one of: its input terminalsy and.' itsoutput terminal in series. withan associated controlling gate circuit G6,1G7

andV G8 respectivelyV betweenthe readA unit 19 Vand the write. unit: Z0. ofthe storage. tube so asv to provide, in

accordancerwithf the settingI of such gate/circuitsgthree andthe other from an externalsource, normally the active address ofthermain storeMS.. In. addition a further con,-

nectionbetween the read unit 19- and the write unitk Ztl is provided by way-'of'. a simple gatev circuit G5, so that when. necessary, simple regeneration ofA the contents` of theraccurnulator. storagetube 16, without any arithmetical operation,.can be effected by opening this gatecircuit and closingeachof the others.V

The actual form. of the computing. circuits 21, 22 and Y 23 is immaterial tovthe, present invention but as examples of suitabletypes. of. device, the computing circuit'Zl may comprisemeans for adding the number wordsrepresented byftwo pulse signal trains` as described'with reference to Fig. 'Z of. ther drawings inl copendingV application of Frederic C. WilliamsY etI al1, Serial No. 141,176 tiledY January V30,. 1950.- The computing circuitV 22 may similar-ly consist ofjmeans` for. subtractingthet numbers represented by. the input pulse signalrtrains and may take av form similar to` that described with reference tov Fig. 13 of. the drawings inV the aforesaid copending, applica-tion, SerialzNo. 141,176. The computing'circuit23maycomprisemeans. for multiplying the two numbers. represented by the input. pulse. trains. and. may take. aY form similar to the multiplier previously described in copending application of Arthur A.. Robinson, Serial No. 132,579, led December 12,. 1949,. now Patent No. 2,685,407, issued August 3,. 19.54. It will. be understood. that other forms of computing circuit, adapted to perform similar or. other types, of mathematical operationsrmay be provided instead'` of those referred to or additional thereto under the Acontrol VofY one ormore further gate circuits.

As. shownV-inEig. 14 the threefcomputingf circuitszl, 22

unit.19 ofthe. accumulator A While the four gatecircuits G5,..G6, G7 and GS.- determine whether thesignal output from vthe. read unit. is. simply regenerated when gatecir cuit. GS.. isopenqandrthe. reminder of.. the. gate.. circuits are.

' closedrwhetherthe signal' outputromthe read unit 19..

isv added to. the. signal from the outward transfer gate Y O'fIGwhen` gate circuitGis open andthe remainder are closed or. whether the signalV output from. the read unit 19fhas-.the external', signal from the gate OTG'subtractedi from it'whenthe gate.Gl7 is'open-and the rest are closedv or whether the two signals from the readunit 19 and from the. gate OTGv respectivelyY are'multiplied together when gate. GSfis open andftheremainder are closed.

Y 'I'heactiorr of these gate circuit-s.y is controlled, in the embodiment. being described, by,I the; particular formlofA the 17th. and 11.8111., digits. of the funetinmdetermtninnpeel.

Vtiroir of. the instructionz word. which inoperative at the.:`

moment and which. has caused. setting up vrof the-maint store staticisorfMSTR.v n Y' Y 7 As. explained-in greater detail inthe-aforesaid: cepend-l ing agnelicat-ion,I Serial No.V 165,434), the staticisorrMSFLR', comprises a pluralityof. similar sections. each comprising: atrigger circuitv and for. thepurposes. of explanation. one

circuit arrangement of one, particular trigger section-of.`Y thefunctionportion FST of suchf staticisor'isfzreproduced:

Diode D3I whose cathodeisv earthed and whose. anodeisV Y connected' to\V the'junction point. w of'resistors R10,R'1I,.

prevents the potential of such junction.- froml rising above..V Y

earthbut doesnotl prevent movement of the; potential; of sucln junction point w in. a negativeV direction. Diode'D4 whose anode is connected-tothe junction point. x otre-- sistors. R12, R13. andl whose cathode. is earthed operates. similarly with referencer tothefpotentialf changes at said last mentioned junction point. Y f Y The quiescent. or binary 0 representing conditionf of thetrigger circuit` is; thatin which valve V1- is conductingfj, Y

to itsy anode: andvalve V2l is cut? oiat its suppressor` grid. 'v Itstriggered or binary 1^ representing condition isithatzV in which theV conditions. are reversed, namely when valve. V1 is. cut off at its-suppressorn grid; andvalvev V2..isyconducting to its anode.

The quiescentrcondition is maintained, or the staticisol`A section is reset to itiif thecircuit has previously-been triggered, at'.. the'. commencement. ofevery scan. beat. by the" applicationof the Halver-A waveform4 to`terminal 31z Thiswaveformis differentiated by condenser CIZTand-rerf`Y sistor R14 and thev negative-going pulse which occurs: at` the beginning of each scan'beat (seeV diagram xiii, Fig. 3) causes: complete. cut off. of kvalve V2 at its: control: grid.. In consequence, if such valve was previously in its triggeredy conditioni and conducting; to its anode, the'v anode .Y potential now;v riseslinthefusual way and this.v rise is come municated to'tle suppressor grid'of valve Vl't'o turn tlre lat-terfon atitsfsuppressor grid and thereby to' cause lower ing', ot the anode potentialv of valve V1', whiclfrlowering: of potential is communicatedbackzto the'. suppressor grid Y of valveVZ to cut thelatter:oiffV ati its. suppressor grid?v as; wellas at its lcontrol grid. When, after decayof theldifferentiated negativegoingpulse: from the: HalverA'. Wave form ati terminal 311;.thefpotentialofv the: control grid': ofi` valvei V21 again' rises, this? valve- V2 becomes:y conductive only to: its'l screen. grid-.andi itssuppressor grid remainsfcut; off bythe potential applied'from-.,valveVl.. The ,diieremtiatedrpositivez-going" pulses produced: at-i the commencef mention each action beatv perio'dibyl the" Halver-A. waveV form vat terminal 31, haveino eflect'as" the control. gridtoff vaIveV-ir is'alreadyY'turned-on:bythatitimeduetotliposi Y Y tive biasl applied through resistor R14'.

Triggering of` the: statici'soi: section into: its. "1 repre-f senting condition. is: effected through themult'iplediodef type gate circuit constituted by diodes 131 D2. and: their.'

Y common cathode resistor R1 which is returnedto saidv voltage. The anode of diode D2 is similarly returned to a source of positive potential (+20 v.) through resistor R3 and is connected to input terminal 32 through which is supplied that particular one of the p-Pulse waveforms which is applicable to the digit position with which the staticisor section is concerned, i. e. the p13, the p14 or the p15 waveform in the present machine. Each of the waveforms applied to the terminals 32, 33 consist of negative going pulses from a normal or resting level of earth potential so that, in the customary manner of operation of such diode gate circuits, depression of the potential of the control grid of valve V1 cannot take place until both of the applied waveforms move negatively simultaneously. This will obviously occur only during the period time of the particular applied p-Pulse waveform and then only if the dynamic instruction or like signal contains a 1 representing pulse at that particular position. When such coincidence occurs the negative potential applied to the control grid of valve V1 causes complete cut-oli of all space current whereby the valve anode potential rises and transmits a positive potential to the suppressor grid of valve V2 and so turns on anode current in that valve. The resultant fall of anode potential at valve V2 is then communicated back to the suppressor grid of valve V1 to hold the latter cut ot at its suppressor grid even when its control grid is again turned on by the disappearance of the coincident negative pulses in the waveforms applied to the terminals 32, 33. This is the triggered or "1 representing condition of the circuit and persists until retriggering takes place at the commencement of the next scan beat as already described.

By reason of the provision of the potentiometer networks of resistors R10, R11 and R12, R13 returned to negative potential (-150 v.) the junction points w and x will move between a potential very slightly above earth, at which they are caught by their related diodes D3, D4 and a potential considerably negative to earth, approx. -60 v. Junction point w will be low, i. e. -60 v. when valve V1 is conducting to its anode in the quiescent or 0 representing condition of the circuit and raised to about earth potential when the valve anode is cut-oit, namely when the circuit is in its triggered or 1 representing condition. Conversely, junction point x will be raised to about earth potential when the circuit is in its quiescent condition and depressed to -60 v. when the circuit is in its triggered condition.

The points w and x are connected respectively to the control grids of valves V3 and V4 arranged as cathode followers with their respective cathode load resistors returned to a source of negative potential (-150 v The cathode of valve V3 is connected to an output terminal /n (sup) and the cathode of valve V4 is connected to an output terminal 1/n (sup). The potential changes at points w and x, which correspond to the suppressor grids of valves V2 and V1 respectively, are thereby made avail- Vable for external controlling purposes, the normal or quiescent condition of the staticisor section providing a potential of 60 volts at terminal 0/n (sup) and 0 volts at terminal 1/n (sup) and the triggered or 1 representing condition of the staticisor section providing a potential of 0 volts at terminal 0/n (sup) and -60 Volts at terminal 1/n (sup).v

The anode of valve V1 is also connected by way of potentiometer network of resistors R15, R16 to a source of negative potential (-150 v.) while the anode of valve V2 is similarly connected by way of potentiometer network of resistors R17, R18 to the same negative potential source. The junction point y between resistors R15, R16 is connected to the control grid of valve V and also to the anode of diode D5 whose cathode is connected to a source of positive potential of +120 volts and to the cathode of diode D6 whose anode is connected to a source of negative potential of volts. The values of the various circuit components are such that when valve V1 isiconducting to its anode, i. e., when the staticisor section is in the quiescent condition, the potential of junction point y falls to and is caught by diode D6 at about -10 volts whereas when the anode of valve V1 is cut off, the potential of junction point y rises to and is caught by diode D5 at about +120 volts. The valve V5 is arranged as a cathode follower with its cathode load returned to a source of negative potential (-150 v.) and has its cathode connected to a further output terminal 0/n which accordingly provides a controlling potential of l0 volts whenever the trigger circuit is in its quiescent or "0 representing condition and a potential of volts when in its triggered or l representing condition.

The junction point z between resistors R17, R18 is similarly connected to the control grid of valve V6 and to diodes D7, D8 which are biased in similar manner to the diodes D5, D6 to limit the potential excursion of the point z to +120 volts when the anode of valve V2 is cut-oit, i. e. when the trigger circuit is in its quiescent condition, and -10 volts when valve V2 is conducting to its anode and the trigger circuit is in its triggered or "1 representing condition.

The address selecting or L-staticisor portion LST comprises a plurality of sections in similar manner to the portion FST and the circuit arrangement of each section is substantially identical with that described above with reference to Fig. 4, except that the four output cathode follower valves V3, V4, V5 and V6 with their associated diode circuits shown below the dotted line in the ligure are omitted and a single output is taken from the suppressor grid of valve V2 to control the operation of the Y-shift generator unit YSG.

One form of circuit suitable for use as any one of the gate circuits G5, G6, G7 or G8 is that of the multiple diode type, as shown in Fig. 5. Such gate circuit com- I prises three diodes D10', D11 and D12, i. e. of a number in accordance with the total number of input signals whose coincidence is necessary before passage of any signal therethrough can take place. Each of the diodes has its cathode connected to one end of a load resistance R10 whose opposite end is connected to a source of negative potential, e. g. volts. The common cathode connection of the diodes conveniently forms an output terminal and is connected, in the example shown, to the control grid of an interposed butler valve V10 arranged as a cathode follower with the output terminal 25 of the gate connected to its cathode. The anodes of the respective diodes D10, D11 and D12 are connected by way of terminals 26, 27 and 28, one to the output from the associv ated computer circuit and the others to suitable terminals on the particular sections of the portion FST of the main store staticisor MSTR so chosen that a suitable negative potential will be applied to each terminal when and only when the particular staticisor sections are set in accordance with the chosen combination of the 17th and 18th digits of an instruction word which calls for the use of a particular computing element.

For illustrative example it will be assumed in the present case that the digit combination 00 for the 17th and 18th digits of an instruction word indicates the desired use of the straight regenerative circuit without any computing operation whatever. To provide this facility terminals 27 and 28 of an arrangement according to Fig. 5 constituting the gate circuit G5 would be connected respectively to the terminal 0/n (sup) of each of the 17th and 18th digit sections of the staticisor MSTR. Only when each of these sections rests in the untriggered or O state will the appropriate negative potentials be applied to each diode anode to allow the negative going signal from the computing circuit to be eiective in changing the potential level at the cathode end of the load resistor.

Similarly the digit combination 10 could be used to indicate desired use of the adding circuit 21 and the corresponding terminals 27, 28 of the gate circuit G6 would, in this instance, be connected respectively to the terminal 1/n (sup) of the 17th digit section and the terminal accumulator to comprise a cathode ray tube electrostatic storage device including a source of an electron beam, control means controlling the activity of said beam and an insulating storage surface in the path of said beam, a pick-up electrode adjacent to said storage surface and an amplifier having its input terminal connected to said pick-up electrode and having an output terminal, an adding circuit device having first and second input terminals and an output terminal for performing an adding operation between two input number-representing signals applied respectively to said first and second input terminals and providing a sum-representing signal at said output terminal, a second computing circuit device having first and second input terminals and an output terminal for performing a subtracting operation between two numberrepresenting signals applied respectively to said first and second input terminals and providing a difference-representing signal at said output terminal, a rst gate circuit having input and output signal terminals and control potential input terminals, a second gate circuit having input and output signal terminals and control potential terminals, circuit means interconnecting the first input terminal of said adding and said subtracting circuit devices to the output terminal of said amplifier, circuit means connecting the output terminal of said adding device to the input terminal of said first gate circuit, circuit means connecting the output terminal of said subtracting circuit device to the input terminal of said second gate circuit, circuit means connecting the signal output terminals of said first and second gate circuits to said control means of said storage device, circuit connecting means between said control potential terminals of said first and second gate circuits and said control output terminals of said staticisor device whereby said first gate circuit can be opened by one conguration of digits of an instruction-representing signal applied to said staticisor device and whereby said second gate circuit can be opened only when another and different configuration of instruction digits is provided in said instruction-representing signal applied to said staticisor device, a first buer circuit having input and output terminals, a second buter circuit having input and output terminals, circuit means connecting the output terminal of said rst buffer circuit to the second input terminal of said adding device, circuit means connecting the output terminal of said second buffer circuit to said second input terminal of said subtracting device and circuit means connecting the input terminals of said first and second buffer circuit to the input terminal of said accumulator unit whereby under the control of an instruction signal supplied from said control unit to said staticisor device, a number represented by a signal fed from said main store may be added to or subtracted from a number represented by a signal derived from said accumulator storage device and the resultant sum or difference answer number-representing signal re-written in said accumulator storage device in the place previously occupied by said derived number-representing signal.

3. ln an electronic binary digital computing machine operating in the serial mode with number-representing signals in the form of electric pulse signal trains and which comprises a main data storage device for recording both number and instruction-representing signals, an accumulator having an input terminal for applying number-representing signals thereto, a control unit for governing the rhythmic operation of the machine and having an instruction input terminal and an instruction output terminal, an instruction staticisor comprising a plurality of separate sections each operative according to the significance of a different digit of an instruction-representing signal and including a common instruction input terminal and a plurality of separate control potential output terminals and circuit interconnections between the output terminal of said main store and the input terminals of said accumulator and said control unit and between s'aidy instruction output terminal of said control unit and said instruction input terminal of said instruction staticisor, said circuit interconnections including a plurality of gate circuit devices controlled by the output potentials of said instruction staticisor, the construction of said accumulator to comprise a cathode ray tube electrostatic storage device including a source of an electron beam, control means controlling the activity of said beam and an insulating storage surface in the path of said beam, a pickup electrode adjacent to said storage surface and an amplier having its input terminal connected to said pickup electrode and having an output terminal, an adding circuit device having first and second input terminals and an output terminal for performing an adding operation between two input number-representing signals applied respectively to said first and second input terminals and providing a sum-representing signal at said output terminal, a multiplying circuit device having first and second input terminals and an output terminal for performing a multiplying operation between two number-representing signals applied respectively to said first and second input terminals and providing a product-representing signal at said output terminal, a first gate circuit having input and output signal terminals and control potential input terminals, a second gate circuit having input and output signal terminals and control potential terminals, circuit means interconnecting the first input terminal of said adding and said multiplying'circuit devices to the output terminal of said amplifier, circuit means connecting the output terminal of said adding device to the input terminal of said rst gate circuit, circuit means connecting the output terminal of said multiplying circuit device to the input terminal of said second gate circuit, circuit means connecting the signal output terminals of said first and second gate circuits to said control means of said storage device, circuit connecting means between said control potential terminals of said first and second gate circuits and said control output terminals of said staticisor device whereby said first gate circuit can be opened by one configuration of digits of an instruction representing signal applied to said staticisor device and whereby said second gate circuit can be opened only when another and different configuration of instruction digits is provided in said instruction-representing signal applied to said staticisor device, a rst buffer circuit having input and output terminals, a second buffer circuit having input and output terminals, circuit means connecting the output terminal of said first buffer circuit to the second input terminal of said adding device, circuit means connecting the output terminal of said second buffer circuit to said second input terminal of said multipiying device and circuit means connecting the input terminals of said rst and second buffer circuit to the input terminal of said accumulator unit whereby under the control of an instruction signal supplied from said control unit to said staticisor device, a number represented by a signal fed from said main store may be added to or multiplied by a number represented by a signal derived from said accumulator storage device and the sum or product answer number-representing signal rewritten in said accumulator storage device in the place previously occupied by said derived number-representing signal.

4. In an electronic binary digital computing machine operating in the serial mode with number-representing signals in the form of electric pulse signal trains and which comprises a main data storage device for recording both number and instruction-representing signals, an accumulator having an input terminal for applying number-representing signals thereto, a control unit for governing the rhythmic operation of the machine and having an instruction input terminal and an instruction output terminal, an instruction staticisor comprising a plurality Y V Y of Yseparatesect-ions Veach',operative accordingly to the Signicance of a dilerent digit Yof an instruction-representingrsignaland including a common instruction input terminal and a plurality of separate control potential outt put. terminals ,and circuit interconnections between the output terminal of said main store and the' input terminals of said accumulator andrsaid control unit and between said instruction output terminal'of said control unit and said instructiony input'terminal of said instruction staticisor, said circuit interconnections including a plurality ofgate circuitdevices controlled by'the output potentials Y' of jsaid instruction Vstaticisor, the 'construction ofV said accumulator to comprise a cathode ray tube electrostatic storageV device Vincluding a sourceof an Velectron beam,

Y control means` controlling Athe activity ofV said beami and an insulating storage surface inthe path of said beam, a pick-up `electrode adjacent, to Vsaid storage surface and an amplilier having its input terminalconnected to said pickup electrode and having an output terminal, a` first com- Y puting circuit device having first and second input ter-Y minals and Voutputltcrminal for performing a chosen first mathematical operationV between two inputV number-representingsignals applied respectively to said ',rst and second input terminals and Vproviding a iirst answerrepresenting signal at said output terminal, a second computing circuit device having rst and second input terminals and an output terminal for performing a sec-j ond, mathematicall operation, diterent from that of saidv lirst computingcircuit device, between two number-repre senting Ysignals appliedrespectively to said first. andjsec- Vond input terminals,v and kproviding a second answer-representing signal at Vsaid output terminal, first, second andV third gatecircuit each having input and output signal terminals and control potential'input terminals, circuit means; in teICQllnecting the ltirst; input terminal of said tirs-t. and said Second computing circuit devices and the input signal' terminal of said thirdY gate circuit to the j output terminal of; said amplier, circuit means rconnecting the output terminal of said iirst computing device to the-input terminal of said iirst gate circuit, circuit means connecting the output terminal of said second computing circuit device tothe input terminal of said second gate Circuit, circuitV means connecting the signal output terminals of said rst, and `second'and third gate Ycircuits t to said control meansof said storage device, circuit connecting Vmeans between saidY control potential terminals of said rs.t,se.cond and; third gate circuits and said Vcon-V trol output terminals.y of .said staticisor device whereby Said lirst gate circuits can be, opened only by'a iirst con.

Y`figuration of digitsof Vaninstruction yrepresenting, signal applied to; said Vstaticisor device andk whereby saidY sec-V Y ond gate circuit can beopened only when a second and different 'congurationy of instructionldigits VVisv provided in saidV insduction-representing Asignal applied to Asaid staticisor device and whereby said third gate l,circuit is Y Y closed wheneversaidrst .or'second configuration ofrinstruction digits isA provided in saidV instruction representingY signal, a iirst buierhaving yinput` and output tert initials, a second buier circuit having input'and output Y Yterminals, circuit meansconnecting the output terminal 1 of saidiirst buffer circuit tothesecond input'Y terminal of said first computing, device, circuit means connecting the output terminal of said second buffer circuit Vto said second input terminal of said secondV computing device @Y and circuit means connecting the input terminals of, said lirsjt and second buier circuit tothe inputl terminalV ofY VsaidV accumulator unit whereby underqthe controlrof an instruction signal supplied from said control'unit to said staticisor device,y a number represented by` a VsignalV fed from said main store, may be .mathematically combined inreither of two different ways with alnumberfrep'resenting signal'derivedfrom said accumulator storage deviceY and the resultantxanswer number-representing signal re- Y written in said accumulator storage device in the place tember 1947, pages -83. Y Digital Computer Switching Circuits, C.' H. Page,

OTHER ReplantationsV Y fA Memory- Tube, Andrew Hael, Electronics, Sep- Electronics, September 1948, pages -118.

A Digital Computer for Scientific Applications, C.

F. West and I. E. De Turk, Y'Proceedings of the IRE., December 1948, pages 1452-1460.

Phelps et al. ,.i July 22, 1952V 

